The present invention relates to integrated circuit (IC) interfacing methods and apparatuses. More specifically, the invention relates to integrated circuit interfacing circuitry that may be reused in multiple applications.
Today's competitive semiconductor companies are constantly having to develop cost reducing manufacturing processes. Large sums of money are invested in the design, integration and testing stages of IC manufacturing. In an effort to reduce the cost of redesigning entire IC designs from scratch, some organizations have implemented an aggressive program designed to create fully tested, and characterized IC designs that may be reused in multiple projects. The IC designs are called "cores," and are employed in, for example, Core Ware.RTM. designs of LSI Logic, Corporation ("LSI Logic") of Milpitas, Calif. (the assignee of the present application).
By way of example, a "core" is a hardware layout of a substantially self-contained integrated circuit module for conducting data processing such as a CPU, an Asynchronous Transfer Mode (ATM) unit, a memory unit, a network interface, an audio decoder, a video decoder, etc. The physical core has associated therewith a core design which specifies a collection of mask layouts used to generate the reticles for photolithography steps employed during integrated circuit fabrication. The core design also includes certain processing parameters associated with masks, such as ion implant energy and dose, etch conditions, oxidation conditions, chemical vapor deposition conditions, etc. Still further, the core design includes information specifying the core interface parameters such as the types of input and output signals required, the locations of the various interface connections, etc.
Various cores may be provided in a library such at the CoreWare.RTM. library of LSI Logic. Such libraries greatly facilitate design of application specific integrated circuits (ASICs), particularly multi-core systems on a single semiconductor chip (sometimes referred to as "systems on a chip"). A system on a chip may include, for instance, a microprocessor core (i.e., CPU core), a video decoder core, and an audio decoder core: all taken from a CoreWare.RTM. library.
Although design costs have been reduced through the implementation of core libraries, an exceedingly large amount of cost, time and effort is spent in integrating the various cores together to form a properly integrated system-on-a-chip. By way of example, when various cores are designed on an IC chip, interface logic including the communication protocols, the timing requirements and the physical interconnections between cores and interface buses must be designed, laid-out, characterized, calibrated, and tested. This process is generally very costly and time consuming.
Even though similar system-on-a-chip designs were created in past applications, a new system-on-a-chip design will generally require engineers to complete the interface logic integration from scratch. This is particularly wasteful where future applications implement similar or substantially similar cores. By way of example, one application may require a Pentium.RTM. processor core from Intel Corporation of Santa Clara, Calif. The processor core is then integrated into the chip by provided the appropriate interfacing logic. Interface logic may include the design of bus interface units (BIU) to communicate with CPU buses, integration necessary to connect a CPU co-processor, integration necessary to connect data/instruction cache units, and so on.
As can be appreciated, a substantial amount of resources may be invested in integrating a Pentium.RTM. processor core into a prior application. Unfortunately, a future application requiring a different Intel processor core may require integration engineers to march through the entire integration process again. There may also be circumstances where future applications will require slightly different processor cores, but reuse the identical CPU bus, memory bus, and memory cores as in a past application. Although the various components remain the same, conventional processes will require engineers to redesign the entire interface logic from scratch.
In view of the foregoing, it would be desirable to implement a design procedure for reusing a prior application's interface logic in a substantially similar future application in order to reduce the engineering and time expenses associated with redesigning the entire interfacing logic from scratch each time a new system is needed.